Modern integrated circuit (IC) die, such as a System on a Chip (SoC), may include millions of MOS transistors on the same die. These transistors are not necessarily identical in structure or use, but rather are divided into multiple blocks of transistor device types with different operational characteristics. Common transistors include analog/digital transistors, high/normal/low frequency transistors, transistors configured to mimic older transistor designs (i.e. legacy transistors), transistors designed to work at distinct voltages, and low/high power transistors, for which the transistors may be of planar MOS type and may be NMOS and PMOS. Alternative transistor designs may be DDC, FinFET or other designs. However, process flows that allow for multiple transistor device types on the same wafer or die are generally difficult to develop and can have relatively low yields. Further, such process flows tend to be extremely sensitive to changes in processes, equipment, and other manufacturing factors. Thus, manufacturers typically limit the types of transistors available on a single die and are resistant to altering manufacturing processes, equipment, or other factors. For this reason, manufacturers would prefer to implement transistors on a common process integration platform, for instance, all transistors being planar MOS type. Additionally, upgrading SoC designs to accommodate improved transistor designs, manufacturing equipment, or processes is generally not preferred due to the expense and risk of new circuit designs that are likely necessary. In view of the foregoing, designers of SoCs and other types of multi-transistor ICs often resort to reusing otherwise inferior or older transistor device types and processes in order to reduce costs and risks for the design and manufacturing of such ICs. The designer is forced to compromise performance and functionality for the sake of cost and manufacturability.